This invention relates, in general, to digital decoding systems and more particularly, to a metal oxide semiconductor (MOS) integrated circuit address decoder.
An integrated circuit memory such as a 16K RAM memory, for example, will have at least 128 rows and 128 columns of cells which must be selected by the address decoders. NOR gates are normally used to achieve such decoding. However, as many as seven inputs may be required for such a NOR gate. The rows and columns of storage cells of the memory are very closely packed together and one NOR gate is required for each row of storage cells to be selected. Consequently, the NOR gates must be no wider, in terms of chip area, than a row or column of cells. It would be very desirable if fewer than six to seven input transistors were required for each NOR gate. There is ordinarily quite a bit of wasted space in the layout of a memory chip in that portion of the chip in which the address inverters or address buffers are located. By now, it should be appreciated that it would be desirable to reduce the number of inputs to the NOR gates and to better utilize the wasted space in the layout of a memory chip.
U.S. Pat. No. 4,027,174 which issued to Yoshihiro Ogata is a good example of the prior art address decoder NOR gates. U.S. Pat. No. 4,027,174 illustrates the large number of inputs required for the address decoder NOR gate. Since this decoder must be squeezed in between the rows and columns of the storage cells it can be seen that sometimes the size of the transistors in the NOR gate must be decreased which also tends to decrease the operating speed of the NOR gate.
Accordingly, it is an object of the present invention to provide an improved circuit for decoding address signals to a memory array.
Another object of the present invention is to reduce the capacitance load seen by the address buffers.
Yet another object of the present invention is to make maximum utilization of silicon space surrounding an IC memory.
A further object of the present invention is to provide predecode addressing for an integrated circuit address decoder.